Research and Development Engineer (Field-Programmable Gate Array FPGA Engineer)

Penn State University

University Park Campus
Date Announced:
Date Closing:
open until filled
Job Number:
Level/Salary Band:
  • 02 – M – Exempt
  • 03 – N – Exempt
Work Unit:
Applied Research Laboratory
System Design
Full/Part Time:


The Undersea Systems Office (USO) at the Applied Research Laboratory (ARL) is looking for a junior or mid-level engineer to join our System Design Department. Responsibilities include: Design embedded hardware using FPGAs and Microprocessors/Microcontrollers with high speed Ethernet interfaces to other subsystems used within Autonomous Underwater Vehicles (AUVs); write Interface Control Documents (ICD) to facilitate communication with Software Engineers and other team members; generate schematics using Altium, work with mechanical engineers in order to develop packaging and thermal control solutions, and guide dedicated board layout personnel; procure or work with others to guide procurement of Printed Circuit Board (PCB) assemblies; write and review procurement specifications to insure performance of completed PCB assemblies; write test and analysis software required to verify hardware functionality, using NI, MATLAB, in Windows and/or LINUX; develop board and subsystem level test procedures, perform testing, and train engineering support staff to perform repetitive testing; perform hands on testing and troubleshooting; and work with team members in order to integrate subsystems. This job will be filled as a level 2, or level 3, depending upon the successful candidate's competencies, education, and experience. Typically requires a Bachelor's degree or higher in an Engineering or Science discipline or higher plus two years of related experience, or an equivalent combination of education and experience for a level 2. Additional experience and/or education and competencies are required for higher level jobs. A Bachelor’s degree in Electrical Engineering or Computer Engineering is desired. The following is preferred: Familiarity with Xilinx Vivado tools; a working knowledge of LINUX and MATLAB and their Xilinx System Generator; skills in Perl, Python, and C/C++; and experience with analog design in the areas of low noise amplifiers, filtering and requirements for driving ADCs in a low power low noise environment. The following are requirements: Fluency in embedded design using hard and soft processors in FPGAs; familiarity with FPGA signal processing techniques; experience crafting designs with networking protocols (TCP and UDP, specifically); experience in full development cycle from HDL code development and board layout through fabrication, assembly, and test; project experience with data conversion blocks (ADCs, DACs); the ability to document work for design re-use and for communication with other team members; and proven troubleshooting skills. All work will be performed within a team environment, which requires strong interpersonal and self-management skills. Travel to remote testing locations to aide in system level testing is required. Candidate selected will be subject to a government security investigation. You must be a U.S. citizen to apply. Employment with the Applied Research Laboratory will require successful completion of a pre-employment drug screen. This is a one-year, fixed-term renewable appointment.

These salary bands have been established to provide salary guidelines for staff positions.

Salary Band Minimum Midpoint Maximum
A $16,584 $24,456 $32,328
B $18,240 $26,904 $35,556
C $19,728 $29,592 $39,456
D $21,708 $32,568 $43,416
E $24,312 $36,468 $48,612
F $27,228 $40,848 $54,456
G $30,012 $45,744 $61,500
H $34,188 $52,140 $70,080
I $38,988 $59,424 $79,908
J $43,716 $67,740 $91,812
K $50,712 $78,600 $106,488
L $58,836 $91,176 $123,528
M $68,232 $105,756 $143,292
N $80,508 $124,788 $169,068
O $93,492 $147,252 $201,024
P $110,340 $173,760 $237,192
Q $126,396 $199,056 $271,728
R $151,668 $238,872 $326,088